When performing signal transmission between two devices that are driven by respective different power supplies, a bidirectional buffer (also referred to as “transceiver”) is sometimes interposed between the devices in order to prevent breakdown of the devices. According to such a method, either one of the two power supplies can be connected to the enable terminal of the bidirectional buffer (also referred to as “transceiver”) to protect the device of the system that is powered off.
FIG. 10 is a block diagram illustrating an example of the configuration of a conventional first information processing apparatus. The information processing apparatus includes a power supply 11 (first voltage generating circuit), a DC-DC converter 12 (second voltage generating circuit), a service processor 13 (first circuit), an ASIC (Application Specific Integrated Circuit) 14 (second circuit), and a bidirectional buffer 15 (buffer circuit).
The service processor 13 has I2CBUS_A which is composed of an I2C (I Square C) BUS, a two-wire bidirectional interface for external communication. Similarly, the ASIC 14 has I2CBUS_B which is composed of an I2C BUS for external communication.
FIG. 11 is a circuit diagram illustrating an example of the configuration of the bidirectional buffer. The bidirectional buffer 15 relays communication between the I2CBUS_A of the service processor 13 and the I2CBUS_B of the ASIC 14. The bidirectional buffer 15 is composed of tri-state buffers 21a and 21b. The tri-state buffers 21a and 21b are powered by VCC1. VCC2 is input to the enable terminal of each of the tri-state buffers 21a and 21b. 
When VCC2 input to the enable terminal exceeds a predetermined threshold and becomes H (High), the signal input from the I2CBUS_A is output to the I2CBUS_B and the signal input from the I2CBUS_B is output to the I2CBUS_A. When VCC2 input to the enable terminal falls below a predetermined threshold and becomes L (Low), the I2CBUS_A and the I2CBUS_B are cut off. It should be appreciated that the enable terminal of the tri-state buffer 21b may be supplied with inverted VCC2.
FIG. 12 is a timing chart illustrating the operation of the conventional first information processing apparatus. The timing chart depicts, from the top, the waveforms of AC power, a primary DC voltage, VCC1, a power-on instruction, and VCC2. Initially, when the AC power is input to the power supply 11 and a power breaker is turned on, the power supply 11 supplies the resident power source VCC1 to the service processor 13 and supplies the primary DC voltage to the DC-DC converter 12.
Next, the service processor 13 which is activated by VCC1 sends a power-on instruction to the DC-DC converter 12. Receiving the power-on instruction, the DC-DC converter 12 supplies VCC2 to the ASIC 14 and supplies VCC2 to the enable terminal (ENABLE) of the bidirectional buffer 15. Here, VCC2 rises and falls gentler than the changes of the signals.
Next, description will be given of the case where unidirectional communication is made from one device to another.
FIG. 13 is a block diagram illustrating an example of the configuration of a conventional second information processing apparatus. In the diagram, the same reference symbols as in FIG. 10 will designate components identical or equivalent to those illustrated in FIG. 1, and description thereof will be omitted. The diagram, as compared to FIG. 1, includes a transmitting unit 23 (first circuit) instead of the service processor 13, a receiving unit 24 (second circuit) instead of the ASIC 14, and a unidirectional buffer 25 (buffer circuit: also referred to as “driver”) instead of the bidirectional buffer 15. The transmitting unit 23 has a terminal of a signal SIGNAL_A to be transmitted outside. The receiving unit 24 has a terminal of a signal SIGNAL_B to be received from outside.
FIG. 14 is a block diagram illustrating an example of the configuration of the unidirectional buffer. The unidirectional buffer 25 relays between SIGNAL_A and SIGNAL_B. The unidirectional buffer 25 is composed of a tri-state buffer 21c which is controlled through the enable terminal. The tri-state buffer 21c is powered by VCC1. VCC2 is supplied to the enable terminal of the tri-state buffer 21c. 
The operation of the second information processing apparatus is the same as in FIG. 12. Initially, when the AC power is input to the power supply 11 and the power breaker is turned on, the power supply 11 supplies the resident power source VCC1 to the transmitting unit 23 and supplies the primary DC voltage to the DC-DC converter 12.
Next, the transmission unit 23 which is activated by VCC1 sends a power-on instruction to the DC-DC converter 12. Receiving the power-on instruction, the DC-DC converter 12 supplies VCC2 to the receiving unit 24 and inputs VCC2 to the enable terminal (ENABLE) of the unidirectional buffer 25.
When VCC2 input to the enable terminal exceeds a predetermined threshold and becomes H, the signal input from SIGNAL_A is output to SIGNAL_B. When VCC2 input to the enable terminal falls below a predetermined threshold and becomes L, the signal input from SIGNAL_A is not output to SIGNAL_B but interrupted.
Among conventional technologies pertaining to the present invention is an output buffer circuit that prevents the occurrence of a leak current and can output a voltage up to an applied voltage quickly when a voltage higher than its own power supply voltage is applied to a common bus.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2000-151383
Now, when the power supply connected to the enable terminal of the bidirectional buffer is turned off, the voltage of the power supply falls slowly due to load capacitances, so that the intermediate potential state can sometimes last long. In such cases, noise occurs at the input and output ends of the bidirectional buffer, sometimes causing system malfunction.
FIG. 15 is a timing chart illustrating an example of the operation of the conventional bidirectional buffer. The timing chart illustrates the operation of the bidirectional buffer in the operation of the first information processing apparatus illustrated in FIG. 12, depicting the waveforms of VCC1, VCC2, ENABLE, I2CBUS_B, and I2CBUS_A from the top. The connection described above makes VCC2 and ENABLE equal to each other. VCC1 from the power supply 11 rises initially, and then ENABLE rises along with the rise of VCC2 from the DC-DC converter 12.
When VCC2 and ENABLE reach a prescribed voltage, I2CBUS_A and I2CBUS_B become operable. Next, when the DC-DC converter 12 is powered off, ENABLE gradually falls with VCC2. Since the intermediate potential state of VCC2 and ENABLE lasts long, noise occurs in I2CBUS_A in the intermediate potential state.
Similarly, when the power supply connected to the enable terminal of the unidirectional buffer is turned off, the voltage of the power supply falls slowly due to load capacitances, so that the intermediate potential state can sometimes last long. In such cases, noise occurs at the output end of the unidirectional buffer, sometimes causing system malfunction.
FIG. 16 is a timing chart illustrating an example of the operation of the conventional unidirectional buffer. The timing chart illustrates the operation of the unidirectional buffer for the same operation of the second information processing apparatus as that of the first information processing apparatus illustrated in FIG. 12, depicting the waveforms of VCC1, VCC2, ENABLE, SIGNAL_A, and SIGNAL_B from the top. VCC1 from the power supply 11 rises initially, and then ENABLE rises along with the rise of VCC2 from the DC-DC converter 12.
When VCC2 and ENABLE reach a prescribed voltage, SIGNAL_A and SIGNAL_B become operable. Next, when the DC-DC converter 12 is powered off, ENABLE gradually falls with VCC2. Since the intermediate potential state of VCC2 and ENABLE lasts long, noise occurs in SIGNAL_B in the intermediate potential state.
The present invention has been achieved in order to solve the foregoing problems, and it is an object of the present invention to provide a relay circuit, an information processing apparatus, and a relay method that prevents the occurrence of noise that results when the enable terminal of a buffer for relaying between circuits enters an intermediate potential state.